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Description

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect branch predictors for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

PUBLISHED Reserved 2024-09-19 | Published 2025-05-13 | Updated 2025-11-03 | Assigner intel




MEDIUM: 5.7CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N
MEDIUM: 5.6CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N

Problem types

Information Disclosure

Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution

References

www.openwall.com/lists/oss-security/2025/05/13/7

comsec.ethz.ch/...arch/microarch/branch-privilege-injection/

lists.debian.org/debian-lts-announce/2025/05/msg00021.html

intel.com/...en/security-center/advisory/intel-sa-01247.html

cve.org (CVE-2024-45332)

nvd.nist.gov (CVE-2024-45332)

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