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Description

Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.

PUBLISHED Reserved 2025-01-16 | Published 2025-08-12 | Updated 2025-08-14 | Assigner intel




HIGH: 7.0CVSS:4.0/AV:L/AC:L/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N
HIGH: 7.9CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

Problem types

Escalation of Privilege

Improper Handling of Overlap Between Protected Memory Ranges

References

intel.com/...en/security-center/advisory/intel-sa-01311.html

cve.org (CVE-2025-22889)

nvd.nist.gov (CVE-2025-22889)

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