CVE-2025-45006

Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

PUBLISHED Reserved 2025-04-22 | Published 2025-07-01 | Updated 2025-07-02 | Assigner mitre

References

github.com/chipsalliance/rocket-chip.git

lf-riscv.atlassian.net/...69/RISC-V+Technical+Specifications

github.com/...in/RISCV/Rocket-chip/CVE-2025-45006/details.md

cve.org (CVE-2025-45006)

nvd.nist.gov (CVE-2025-45006)

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