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Description

The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.

PUBLISHED Reserved 2025-07-23 | Published 2025-11-23 | Updated 2025-11-24 | Assigner AMD




LOW: 1.0CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N

Problem types

CWE-1284 Improper Validation of Specified Quantity in Input

Product status

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

Default status
affected

2025.2
unaffected

References

www.amd.com/...es/product-security/bulletin/amd-sb-8020.html

cve.org (CVE-2025-54515)

nvd.nist.gov (CVE-2025-54515)

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