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LOW: 1.0 CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:NDefault status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Default status
affected
2025.2
unaffected
Description
The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Problem types
CWE-1284 Improper Validation of Specified Quantity in Input
Product status
2025.2
2025.2
2025.2
2025.2
2025.2
2025.2
2025.2
2025.2
References
www.amd.com/...es/product-security/bulletin/amd-sb-8020.html