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Description

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture. RISC packages risc0-zkvm versions 2.0.0 through 2.1.0 and risc0-circuit-rv32im and risc0-circuit-rv32im-sys versions 2.0.0 through 2.0.4 contain vulnerabilities where signed integer division allows multiple outputs for certain inputs with only one being valid, and division by zero results are underconstrained. This issue is fixed in risc0-zkvm version 2.2.0 and version 3.0.0 for the risc0-circuit-rv32im and risc0-circuit-rv32im-sys packages.

PUBLISHED Reserved 2025-07-31 | Published 2025-08-05 | Updated 2025-08-06 | Assigner GitHub_M




LOW: 2.7CVSS:4.0/AV:N/AC:L/AT:N/PR:N/UI:N/VC:N/VI:L/VA:L/SC:N/SI:N/SA:N/E:U

Problem types

CWE-369: Divide By Zero

Product status

>= 2.0.0, < 2.2.0
affected

References

github.com/.../risc0/security/advisories/GHSA-f6rc-24x4-ppxp

github.com/risc0/risc0/pull/3235

github.com/risc0/zirgen/pull/249

cve.org (CVE-2025-54873)

nvd.nist.gov (CVE-2025-54873)

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