CVE-2025-63384 | THREATINT

Description

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

PUBLISHED Reserved 2025-10-27 | Published 2025-11-10 | Updated 2025-11-12 | Assigner mitre

References

github.com/chipsalliance/rocket-chip.git

github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET

cve.org (CVE-2025-63384)

nvd.nist.gov (CVE-2025-63384)

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