HomeDefault status
unaffected
Any version before r1p2-50eac0
affected
Description
An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
Problem types
CWE-362 Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
Product status
Any version before r1p2-50eac0
References
developer.arm.com/documentation/111823