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Description

An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.

PUBLISHED Reserved 2026-01-15 | Published 2026-03-02 | Updated 2026-03-02 | Assigner Arm

Problem types

CWE-362 Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')

Product status

Default status
unaffected

Any version before r1p2-50eac0
affected

References

developer.arm.com/documentation/111823

cve.org (CVE-2026-0995)

nvd.nist.gov (CVE-2026-0995)

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